I. Field of the Invention
This invention relates to discrete decoupling capacitors utilized as components attached to the surface of a substrate for semi-conductors.
II. Prior Art
Multi-layer ceramic VLSI chip packaging substrates are formed by having a multiple number of flexible unfired sheets of soft ceramic material. These sheets, generally known as greenhseets, have holes or vias punched into them in a known pattern. An electrically conductive paste is then screened through a metal mask to form personalized wiring patterns on the greensheet and to fill its via holes. A completed substrate is fabricated by stacking multiple greensheet layers that are pressed together to form a semi-hard stack or laminate which is then fired. The result is a substrate for VLSI chips.
On the substrate surface, an array of semiconductor chips are mounted with the substrate establishing all electrical connections within and between the chips. On the top surface of the substrate, each chip site is composed of an array of chip contact vias (C4 pads or microsockets). Disposed around each chip site is an area on the substrate for engineering changes, i.e., for wire connections to cure correctable defects in the chip or substrate.
Advanced semiconductor circuits employ decoupling capacitors. The decoupling capacitors are charged independent of circuit operation and are discharged to deliver via the substrate redistribution layer a current that enables fast transition circuit switching with a minimum noise. The elements are conventionally mounted on a circuit board, some distance away from the chip. One desired technique would be the use of a decoupling capacitor as a discrete component that is attached to the surface of the substrate. Closer physical location allows for and is essential for higher switching speeds of the chip. If utilized in that manner, not only is the capacitance of the component important, but additionally, its inductance is crucial to overall performance. The inductance of a discrete capacitor is directly proportional to the number of interconnections between it and the chip-carrying substrate. The larger number of bonds is desirable and results in a lower inductance. Moreover, the closer to the logic chip the capacitor is placed, the lower the inductance.
While a large number of prior art discrete capacitor devices are known, none is believed to be directly pertinent to discrete very low inductance capacitors where the substrate itself contains integrated wiring patterns. None is believed to be pertinent to discrete decoupling capacitors utilized on a support structure that is a multi-layer ceramic having a pattern of conductive wires embedded therein and a multitude of throughhole vias at discrete chip site locations. Prior art thin film capacitors mounted on circuit boards are shown in references such as U.S. Pat. Nos. 3,819,990 and 4,158,218. Techniques of circuit board assembly which may utilize insulative substrates and electrical components including capacitors are typified by U.S. Pat. Nos. 4,139,881 and 4,164,778. Techniques of aligning discrete elements on a substrate are discussed in U.S. Pat. No. 3,811,186. None of the prior art, however, relates to a discrete chip capacitor utilizing pad connections on the substrate and employing thin film processes to match dimensionally, mechanically, and electrically, those facets of the substrate to which the capacitor is joined.